Design of a Simple OFDM IF Transceiver on FPGA
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Abstract
Abstract:
References
Ludwig Schwoerer, "VLSI suitable
synchronization algorithms and architecture for
IEEE 802.1la physical layer", Nokia research
Center. 2002[EEE.
Jamil Ahmad, "A novel fine frequency
Synchronization Technique for OFDM Wireless
Systems", lTtn European Signal Processing
Conference (EUSIPCO 2009).
Hlang Minn, Vijay K.Brargava, Khaled Ben
Letaiei "A robust Timing and Frequancy
Synchronization for OFDM System", IEEE
Transaction on wireless communications,
Vol.2,No.4,July 2003.
M.Jose Canet, Felip Vicedo, Vicenc Almenar,
Javier Valls, "FPGA Implementation of an IF
transceiver for OFDM based wlan", 2004 IEEE
Francisco Cardells Torno, Asun Perez Pascual,
Vicente Torres Carror, Javier Valls Coquillar,
Vicenc Almenar Terre, "Design of a DVB-S
receiver in FPGA", 2003 IEEE.
References
lll
tzl
l3l
t4l
t5l
64 T.T.T. Qulnh et al. / WU lournal of Natural Sciences anil Technology, VoL 29, No. L (2073) 57-54
-. r€*
t6] Danienl Cardenas, German Arevalo, "All
Digital Timing Recovery and FPGA
Implementation", Co. Politecnico, Ecuador,
2005.
I7l Lars Erup, Floyd M.Gardner, Robert A.Harris,
Interpolation in digital Modems-Part II:
Implementation and Performance, IEEE
Transaction on Communications, Vol.4l, No. 6,
June 1993.
synchronization algorithms and architecture for
IEEE 802.1la physical layer", Nokia research
Center. 2002[EEE.
Jamil Ahmad, "A novel fine frequency
Synchronization Technique for OFDM Wireless
Systems", lTtn European Signal Processing
Conference (EUSIPCO 2009).
Hlang Minn, Vijay K.Brargava, Khaled Ben
Letaiei "A robust Timing and Frequancy
Synchronization for OFDM System", IEEE
Transaction on wireless communications,
Vol.2,No.4,July 2003.
M.Jose Canet, Felip Vicedo, Vicenc Almenar,
Javier Valls, "FPGA Implementation of an IF
transceiver for OFDM based wlan", 2004 IEEE
Francisco Cardells Torno, Asun Perez Pascual,
Vicente Torres Carror, Javier Valls Coquillar,
Vicenc Almenar Terre, "Design of a DVB-S
receiver in FPGA", 2003 IEEE.
References
lll
tzl
l3l
t4l
t5l
64 T.T.T. Qulnh et al. / WU lournal of Natural Sciences anil Technology, VoL 29, No. L (2073) 57-54
-. r€*
t6] Danienl Cardenas, German Arevalo, "All
Digital Timing Recovery and FPGA
Implementation", Co. Politecnico, Ecuador,
2005.
I7l Lars Erup, Floyd M.Gardner, Robert A.Harris,
Interpolation in digital Modems-Part II:
Implementation and Performance, IEEE
Transaction on Communications, Vol.4l, No. 6,
June 1993.