Demonstration on Ferroelectric-gate Thin Film Transistor NAND-type Array with Disturbance-free Operation

Abstract

Abstract: A novel concept of NAND memory array has been proposed by using only ferroelectric-gate thin film transistors (FGTs), whose structure is constructed from a sol-gel ITO channel and a sol-gel stacked ferroelectric between Bi_3.25La_0.75Ti₃O₁₂ and PbZr_0.52TiO_0.48O₃ (BLT/PZT) gate insulator. Interestingly, ferroelectric cells with a wide memory window of 3 V and a large on/off current ratio of 6 orders, have been successfully integrated in a NAND memory circuit. To protect data writing or reading from disturbance, ferroelectric transistor cells are directly used, instead of paraelectric transistor cells as usual. As a result, we have verified disturbance-free operation for data reading and writing, with a small loss of the memory state and a low power consumption, in principle.

Keywords: ITO, PZT, NAND, FeRAM, ferroelectric.

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